An integrated circuit (IC) is a set of electronic circuits that integrates a large number of semiconducting transistors into a small chip. Among the most advanced integrated circuits are microprocessors, memory chips, programmable logic sensors, power management circuits, etc. Advances in IC technology have led to size reduction of transistors, enabling greater densities of devices and circuits in IC chips and enhanced performance. Over the years, because of the ever-increasing complexity of IC designs, IC designers have become more and more reliant on electronic design automation (EDA) tools to assist them in designing ICs. Assistance from the EDA tools spans the entire design process, from synthesis, placement, routing, to layout verification.
A common method of designing an IC requires that an IC designer first have a library of circuit cells and a design describing the functionality of the integrated circuit. The cells may implement fundamental logical functions such as OR, NAND, NOR, AND, XOR, inverter. The cells may also include sequential circuit elements such as latches and flip-flops for memory requirements. The library of circuit cells may be provided by a fabrication vendor and are specific to the vendor's fabrication process technology. For most cell functions, the library offers a number of different cells optimized for different purposes.
Placement and routing is a stage in the design of ICs that involves two steps. The first step, placement, involves deciding where to place the cells in an IC layout that has a limited amount of space. The selection of cell placement is usually made on the basis of factors such as minimum and maximum setup and hold times, cell power consumption, size of the cells, routing and interconnect delays between different cells, and leakage current. It is an iterative process to select cells that optimize over an entire module or chip. The placement step is followed by routing, which decides the exact design of all the wires needed to connect the placed cells in the layout. The routing step implements all the desired connections while following the rules and limitations of the manufacturing process. The final product of the two steps process is a final layout, a geometric description of the shapes in and the location of each cell, and the exact path of each wire connecting them.
In earlier technologies, transistor sizes were large enough that their electrical behavior was independent of their locations in the final layout. However, in highly scaled technologies with smaller geometries, the electrical performance of a transistor has become increasingly dependent (˜40-50% more dependent) on its location in the layout. Intentional stresses and unintentional stresses in the layout, as well as unwanted variations in intentional stresses, affect the electrical properties of the transistor due to electronic band deformation of various materials used in integrated circuits and change in electron and hole mobility in transistors. Thus, it becomes imperative to consider the contributions of various intentional and unintentional stress generation mechanisms near a transistor to analyze its performance accurately. As used herein, a “stress generation mechanism” is one that may cause stress variations within one cell and in other cells.
Examples of intentional stress generation mechanisms which improve mobility of electrons and holes include source/drain regions with alloys that have a bigger lattice constant than silicon, dielectric nitride films with intrinsic compressive or tensile stress grown over a transistor region, deposition and removal of sacrificial polysilicon gates and subsequent metal gate deposition, stress incorporated in the metal contacts over source/drain regions, etc. Due to process variation during IC manufacturing, there may be variations in intentional stress generation mechanisms in the IC.
In addition to variations in intentional stress generation mechanisms, unintentional stress generation mechanisms in the layout also interfere with the engineered intrinsic stress and cause placement-dependent electrical parameter variations in the final IC. The unintentional stress generation mechanisms can mainly be attributed to the thermal mismatch of various materials used during IC manufacturing. Major sources of unintentional stress that lie in proximity of the transistors in integrated circuits are shallow-trench isolation or STI (used to isolate transistors in the layout), through-silicon-vias or TSVs (used for making vertical interconnections between stacked ICs), mismatch between package substrate and silicon die, “cutting” of fins in FinFETs to break long fins into individual pairs or to create an isolated fin, fin edge effects in FinFETs, etc.
Intentional and unintentional stress generation mechanisms significantly affect design methodologies in modern integrated circuits, which are built from a pre-characterized library of cells. These cells may be instantiated multiple times in different parts of the final layout, where they experience different stress variations. Stress effects in a layout are relatively complex because of directional dependency, variation in material sources, and sensitivity to the placement of cells. Each layout feature in a cell, such as the edges or corners of various parts of the transistors in the cell, STI or TSVs, contributes to stress variation with an interaction range of up to 2 microns. Therefore, a stress generation mechanism in a first cell can contribute to stress variation in other cells in the layout in the vicinity (˜2 microns) of the first cell. Performance of the first cell at a certain placement in a layout is not only dependent on the internal stress generation mechanisms within the first cell but also on external stress generation mechanisms in neighboring cells. Similarly, the performances of neighboring cells are also affected by the internal stress generation mechanisms of the first cell. It may well be, for example, that a cell chosen for a particular function for insertion into a particular position in a layout, has its performance changed so substantially due to stresses imposed by neighboring cells, that the chosen cell may actually be the wrong cell for the particular function.
In the above-incorporated U.S. patent application Ser. No. 15/901,749, filed Feb. 21, 2018, entitled Automated Resistance And Capacitance Extraction And Netlist Generation Of Logic Cells, a Design-Technology Co-Optimization technique is described with a goal of developing a Power-Performance-Area evaluation of a library cell based on its GDS layout and process flow. Realistic parasitic RC values are extracted for the specific 3D structure of a library cell, including lithography and etch micro-loading effects, and the cell is characterized using a circuit simulator such as HSPICE. However, BSIM compact SPICE models are extracted for a nominal transistor only, which does not account for stress, lithography, etch micro-loading and other cell proximity effects that can contribute as much as 30% or more to cell performance variations.
In the past, in order to account for cell layout proximity effects in the evaluation of cell performance, it was typical to use a Design Rule Check tool (like ICV (Integrated Circuit Validator) from Synopsys) to measure several hundred distances from each transistor of the cell to its neighbors. These distances were used in look up tables to determine modifications of the nominal BSIM parameters for each specific transistor in the circuit, such as a shift in Vt (threshold voltage) or change in mobility. This methodology required a huge effort, including thousands of test structures that try to mimic all possible layout configurations, and including calibration of an appropriate set of look-up tables and implementing look-up table evaluation into circuit analysis tools like HSPICE. The difficulty in making this approach work again limits its availability to only in the later stages of technology development as part of a mature Process Design Kit (PDK). It is not available in the early stages of technology development, where a DTCO tool flow provides co-optimization of technology and design.